I may not be smart enough to understand, but I want more clarity.
They're licensing NVLink C2C, right? But what's the benefit for companies with custom ASICs and why would they use it? Access to Grace CPU or NVLink 5? AFAIK the first is kind of meh. The second is cool, but why would they go for NVLink 5 instead of what they use now (I assume Broadcom)?
We've seen the same in the gaming side, with their own proprietary stuff. G-Sync was first to market and proprietary , and the open spec ended up winning.
We'll see if it works out for them. Nobody like to be locked-in to a single company proprietary shit. It can work some of the time, not sure it will all of the time.
Could you elaborate on this? For me as a mrvl bull it sounds good, but a bit technical:
Then, Alchip fucks up integrating the Synopsys 200G SerDes and has to re-spin. Now rumor is Marvell got the Trn3 IO die even though their 200G SerDes is crap too.
Weren't you impressed with MediaTek's SerDes? Is the probability of success for TPU V7E very low now?
https://irrationalanalysis.substack.com/p/isscc-2025-ultra-high-speed-serdes
I may not be smart enough to understand, but I want more clarity.
They're licensing NVLink C2C, right? But what's the benefit for companies with custom ASICs and why would they use it? Access to Grace CPU or NVLink 5? AFAIK the first is kind of meh. The second is cool, but why would they go for NVLink 5 instead of what they use now (I assume Broadcom)?
interested to hear more insights on this as well...
I think AVGO gets more viable competition for custom AI silicon now instead of winning them all.
This is totally expected form Nvidia
We've seen the same in the gaming side, with their own proprietary stuff. G-Sync was first to market and proprietary , and the open spec ended up winning.
We'll see if it works out for them. Nobody like to be locked-in to a single company proprietary shit. It can work some of the time, not sure it will all of the time.
My take (though not understood the domain enough):
1. Scale Up Ethernet(from Broadcom) has the most potetial for wide adoption as scale up fabric solution
2. With SUE and NVLink Fusion in the race, I think UALink may have to merge with SUE via OCP org. Fundamental transport probably be SUE.
3. NVLink Fusion, has too much control by nVidia. QCOM seems to have joined. Will Intel, AMD join? How will it work out?
4. Since it will be an chiplet technology (2.5D or 3D), integrated solutions would be highly involved(my guess)
NVDA investment and partnership with Intel guarantees Intel joining NVLink Fusion IMO.
Could you elaborate on this? For me as a mrvl bull it sounds good, but a bit technical:
Then, Alchip fucks up integrating the Synopsys 200G SerDes and has to re-spin. Now rumor is Marvell got the Trn3 IO die even though their 200G SerDes is crap too.
And what do you think AMD must do, and what will they do?
What about other (smaller) vendors? Like Xsight Labs?
Really no one else has a Good PHY?
So this means that the hyperscalers that use NVLink Fusion chiplet Asics cannot use their own CPU asics?