Extrapolating ASML and TSMC Earnings

State of the semiconductor industry, October 2024

• Irrational Analysis is heavily invested in the semiconductor industry.

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ASML 0.00%↑ caused some volatility is semiconductor stocks last week. There are a lot of bad takes floating around so wanted to write up a better tread-through, sector by sector.

My trading volume last week was greater than all of 2024 combined. Had to make significant changes. A full portfolio update and my best ideas are in section [4].

Contents:

1. ASML Faceplant

2. TSMC Smash Hit

3. State of Play

   1. Leading Edge Logic Fabs

      1. What is a PDK?

      2. What is Parametric Yield?

      3. How PDK and Parametric Yield are Linked

      4. How TSMC, Intel Foundry, and Samsung Foundry Interact with Design Teams

   2. Memory

   3. Semicap

      1. China

      2. TSMC

      3. Intel

      4. Samsung Foundry

      5. Samsung Memory

      6. Everyone Else (Micron, SK, UMC, GloFo, …)

   4. Optics

   5. Smartphone

   6. AI Logic

   7. Laptop/PC

4. Summary of Ideas

   1. Long-term (3-7 years)

   2. Medium-Term (0.5-2 years)

   3. High Risk

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[1] ASML Faceplant

We are off to a great start.

Ah, yes. Still have super high China exposure.

Surely, TSMC won’t try to use their earned monopoly status to negotiate price cuts on EUV and high-NA EUV tools? 😈

He is talking about Samsung Foundry and Intel Foundry.

China finally de-risked from guide. Good.

I don’t buy this narrative that there are “two dynamics”. Samsung Foundry and Intel delaying fabs has a much bigger impact than some weakness in auto/PC.

UBS Analyst is trying to force ASML management to admit their faceplant is largely because of Samsung Foundry and Intel Foundry. I’m not going to include ASML CEO’s response because he dodged again. We all know what is going on. Everyone in this industry knows what is happening.

[2] TSMC Smash Hit

Great N3-family ramp.

HPC remains strong. AI logic to the moon. Smartphone QoQ growth is cyclical.

Intel outsourcing will increase in 2025. Lunar Lake ramp and some datacenter products.

Chiplets are driving scaling these days. I believe the limit to TSMC pricing power depends on chiplets. If N2 cost is too high, more design content will be moved to N3 or even N4P. The insane demand helps a lot of future pricing power and gross margin growth. Otherwise, chiplets would indeed by a major ASP dilutor in the future.

Smartphone is a bit interesting right now. Ming-Chi (TFT International) has some great commentary I want to cover in section [3.e].

[3] State of Play

We have 50 trading days left in the year. Earning season just got started. ASML and TSMC have provided very useful information that can be applied to many other names.

Section [3] is for technical and industry background, so you understand the ideas in section [4] sufficiently before doing your own research.

Do not blindly make investment decisions based on what you read here!

[3.a] Leading Edge Logic Fabs

I consider the leading edge logic fab market to consist of three companies:

1. TSMC

2. Intel Foundry (aka IFS)

3. Samsung Foundry (logic division —> memory it’s own department)

Rapides does not count as they don’t have anything until like 2028 realistically. SMIC is China-only. For what it’s worth, SMIC 5nm-class is remarkably good but has horrible yield. Huawei is severely supply constrained.

TSMC is an earned monopoly. They won their market share (95%+ on leading edge) through superior engineering and (more importantly) disciplined execution.

The N3B node is a great example. As a joke, I like to think the ‘B” in N3B stands for ‘botched’. This node was bad. Only Apple and Intel have used it due to timeline pressures. Everyone else just waited for N3E/P/X/A, the real N3 nodes. N3B is completely different from the other N3-family nodes.

What separates TSMC from their logic foundry competitors is how they responded to their own mistake. TSMC rapidly fixed their 3nm-class nodes in 12-18 months. Intel spent years making the same mistakes over and over in their 10nm disaster. Samsung Foundry is currently on their 4th attempt of making a 3nm-marketed node. 3GAA. 3GAE, and SF3 have all failed. The upcoming node marketed as SF2 is really just a re-name of SF3. SF2 really is Samsung “3nm” attempt #4.

Intel Foundry is trying their best, but they lack experience. I believe if 18A is successful, the earliest 3rd party revenue recognition would be in H2 2026 at best. Realistically, I believe Intel is on their own until 2027.

As for Samsung Foundry, I have very little hope. Massive cultural issues. To understand why, you must first understand what a process development kit (PDK) is.

[3.a.i] What is a PDK?

Process Development Kits contain a huge amount of information that dictates how chip designs are physically implemented. Every individual “device” contains detailed characteristic analysis. From intrinsic resistance, to parasitic capacitance, to frequency response.

For example, the size of transistor cells effects their performance (switching speed), power draw, and area.

Source

Transistors (all devices and structures really) also have parasitics. Unwanted attributes that must be accounted for in the design stage via simulations based on the PDK.

Source Example of parasitic capacitance of a transistor.

Every active device also has IV (current versus voltage) reponses depending on the source supply voltage.

Source: Example IV responses of transistors on a 65nm process node.

Source: Table comparing the intrinsic device characteristics across many process nodes. Every node is different!

Modern, leading-edge node PDKs are very complex. Every individual device, from a wire to large blocks of transistors within a standard cell, is characterized in detail. This is across three primary variables:

1. Voltage

2. Temperature

3. Process

In real systems, the input voltage to a chip is not exactly a fixed DC voltage.

Example of power supply noise. Likely coming from a 500KHz switching regulator.

Another example of supply noise.

Therefore, circuits need to be tolerant to a range of voltages. Say 750mV +/- 40 mV for example.

Temperature response is also important but the level of tolerance a design needs depends on the end-market.

Example of how a transistor gain response changing based on temperature.

For example, chips intended for the automotive and embedded markets typically need to tolerate operating conditions of [-40C, +125C] while a smartphone chip would need to be qualified for a much narrower temperature band. Fun fact… Nvidia NVLink beat everyone to market partially because they don’t need to design to official Ethernet or PCIe specifications. They know NVLink is only going into liquid-cooled datacenters and can thus optimize for operation at [+20C, to +95C].

The final variable is process corners.

Source

Due to how the wafers are fabricated, the speed of the transistors is not uniform across the entire wafer. Thus, some chips have transistors that run faster than or slower than expected.

Source Each wafer has a probability distribution. Some chips will be faster/slower than others.

Source

The PDK provides vital information designers need to simulate circuit stability and performance across real-world operating conditions, AKA “corners”.

• Hot/Cold

• Fast/Slow NMOS

• Fast/Slow PMOS

• High/Low Voltage

Here is how the notation works.

TT NTNV = TT process corner + nominal temperature + nominal voltage

Voltage is often a band. Say target of 0.75 +/- some %.

The process corner characteristics (SS, FF, SF, FS) are modeled in the PDK with many intrinsic variables shifted. Capacitance, inductance, rise time, leakage, … and so on.

[3.a.ii] What is Parametric Yield?

Given the wide range of conditions a chip needs to function at, it is expected that some percentage will fail and thus cannot be sold.

The percentage of chips that pass quality and reliability checks is called parametric yield.

Think of the process corner diamond as a dartboard. The Fab wants to hit darts (portions of wafers) in the center. But they are not perfect.

Illustrative example scatterplot of chips from multiple batches. Each color group represents chips from a distinct group of wafers.

Production-speed wafers go too fast for the process corner of a chip to be known reliably. Ring oscillators (simple health-check circuits) can help estimate directionally what corner a chip might be, but not with much certainty.

To enable R&D, Fabs run special shuttles of wafers slowly through the process to intentionally over/under dope specific sections of test wafers. These engineering sample chips are then labeled with a-priori process corner information. The Fab customer knows ahead of time what corner each test chip is from.

Illustrative example scatterplot of test chips from special R&D shuttles. A-priori knowledge of the process corner and ring oscillator speed/health are used to check how skewed a particular chip is.

[3.a.iii] How PDK and Parametric Yield are Linked

In the design stage, engineers have to rely on the PDK to over-build circuits such that most of the production chips pass spec at all PVT (process, voltage, temperature) conditions. Spec can mean a lot of things so lets say our fake example spec is the following:

1. All functionality passes.

2. 0.75V supply voltage.

3. 1.2 GHz target clock frequency.

4. 5 watt power draw (TDP)

Suppose engineers use the PDK to simulate how their design will perform and estimate that 70% of chips will pass spec (0.75 VDD, 1.2GHz, <5w).

The chips come back and only 50% pass spec. With some tuning, the parametric yield number is brought up to 60%.

Now the design company has an economic choice to make. Sell only 60% of production chips (instead of the planned 70%) and accept lower gross margins due to higher COGS, or… alter the spec.

Can 70% of chips pass at 0.75V, 1.1GHz, <5w?

What about 0.85V, 1.3GHz, <7W?

The point I want all of you to understand is that clock speed, input voltage, and power/thermal requirements are all economic choices in the end.

If the PDK is good, then reaching parametric yield targets is easy. Otherwise, panicked tuning and compromises.

There is a word for how this type of data is plotted. A Schmoo plot.

If you raise voltage high enough and lower the performance/frequency bar enough, a larger proportion of chips will “pass”. Obviously, higher voltages harm reliability.

[3.a.iv] How TSMC, Intel Foundry, and Samsung Foundry Interact with Design Teams

Those of you who read the news and keep seeing Samsung Foundry fail with terrible 10-20% yield might be wondering… why?

Why only Samsung? Why not TSMC?

The delta is not technical, it’s cultural.

TSMC has a habit of conveying optimistic assumptions in their public marketing, conference papers, and PDK documentation.

N3 was renamed to N3B later.

Every design will have different scaling depending on many factors such as the logic/SRAM/analog ratio, clock tree, target end market, …

The first thing a design team does is simulate some small standard IP blocks using the new PDK from TSMC. Initial results are often worse than marketing which is fine. Adjustments are made, and eventually chip yields well in production and everyone is happy.

TSMC is benevolently optimistic when sharing PDKs and interacting with customers. All of the simulations in the PDK are firmly grounded in reality. Designers across the industry are experienced at mind-gaming TSMC, spotting suspicious numbers and over-designing as a precaution.

Intel Foundry means well but lacks experience. They have a history of using proprietary internal-only tools and altering the process nodes to requests from internal design teams. Pat “Galaxy-Brain” Gelsinger tried to buy TSEM 0.00%↑ for PDK development reasons, not the lagging-edge process node portfolio. Tower Semi engineers know how to write PDKs and interact with 3rd party design teams. It is very unfortunate the acquisition was blocked. Intel really needed external help with PDK development.

There is overwhelming public evidence that Samsung Foundry has repeatedly and materially mis-represented their process nodes. In other words, PDKs are consistently wrong and this severely harms parametric yield.

Here is a timeline:

What’s remarkable about this whole saga is the level of detail that has been leaked. Yield data is extraordinarily sensitive!

Look at this leak from Ice Universe, a well-known Samsung leaker.

Someone from the Exynos team shared highly sensitive power/frequency data. This leak is a Schmoo plot in verbal form.

I have been obsessively following semiconductors since 2011. Never have I see such detailed leaks of highly-sensitive information.

Parametric yield is bad, and the designers are leaking to let everyone know who they believe is to blame.

The most logical conclusion is Samsung Foundry has repeatedly mis-represented their process node, providing misleading PDK characteristic data to the internal Exynos design team and 3rd party foundry customers.

Samsung Foundry has a cultural problem.

Samsung Electronics Cultural Issues Are Causing Disasters In Samsung Foundry, LSI, And Even DRAM Memory!

Clearly, the situation has not gotten any better.

[3.b] Memory

Memory is fine. For investment purposes, only one thing matters.

Is Samsung going to fix their HBM yield issue?

If that happens, SK and MU 0.00%↑ stocks will both tank. Samsung has massive HBM capacity. They have failed to qualify with Nvidia several times. Even now, only low-volume of HBM3 (not HBM3E) is accepted by Nvidia. AMD has experienced significant manufacturing ramp delays because of thermal issues with Samsung HBM.

It’s the same story as logic foundry. Bad parametric yield.

[3.c] Semicap

Semicap is controversial amongst the investors I talk to. One ultra-bearish guy I know keeps talking about historical book value. Most other investors have some kind of strange cult-like affinity for semicap.

Let’s go over every customer of semicap.

[3.c.i] China

New export controls are going to hit soon. ASML results clearly state this. Management wanted to just say what we all know but legally can’t. They have to wait for the official announcement.

[3.c.ii] TSMC

TSMC has a very strong negotiating position. I think they are going to force ASML to accept price cuts on high NA EUV machines. TSM 0.00%↑ will also go to every other vendor and demand favorable deals, including discounts on service contracts.

Semicap bulls, I am sorry to inform you that TSMC raising CapEx guide won’t save the stocks from all the other headwinds, including price cuts on equipment.

[3.c.iii] Intel

Frankly, the sentiment around INTC 0.00%↑ is bizarrely optimistic. I think Intel is going to be curled up in a ball of agony for the next 12-18 months. Meaningful 3rd party Foundry revenue is H2 2026 at best.

More delays and cuts of CapEx are coming IMO.

[3.c.iv] Samsung Foundry

Unmitigated disaster.

[3.c.v] Samsung Memory

They have plenty of equipment and capacity. Problem is yield. I doubt they will spend much on more equipment. Better to spend the money fixing yields.

[3.c.vi] Everyone ELse (Micron, SK, UMC, GloFo, …)

It’s fine.

[3.d] Optics

I am hyper bullish optics.

You will have to wait at least another month. Sorry.

[3.e] Smartphone

I was bearish Smartphone, but Ming-Chi crushed my QCOM 0.00%↑ short thesis.

PRC stimulus killed my short thesis. I was counting on the average PRC consumer not buying a new phone due to crushing mortgage debt for apartment(s) that don’t exist.

Samsung apparently killing off Exynos 2500 is also very beneficial for both Qualcomm and TSMC. MediaTek is rumored to have gotten the Galaxy S25 FE stocket.

[3.f] AI Logic

To the moon.

[3.g] Laptop/PC

Intel, Microsoft, and all the laptop OEMs tried to push a narrative that AI PC is real. Huge refresh cycle incoming! Windows 10 EOL will drive hardware upgrades!

This narrative was obvious BS and data supports this.

No growth for you!

[4] Summary of Ideas

I had to panic cover my large QCOM 0.00%↑ short at a loss and re-balance risk in my main account.

[4.a] Long-Term (3-7 years)

My highest conviction long-term investment ideas are TSM 0.00%↑ and AVGO 0.00%↑.

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TSMC has an incredible earned monopoly due to superior engineering and failing competitors. Legally, South Korea does not allow short selling. You can’t short Samsung Electronics, but you can go long TSMC,

I believe that TSMC will have zero meaningful competition until 2027 when Intel 18A comes online in a big way. Even then, TSMC will remain dominant until Intel 14A.

Here is a detailed breakdown of which projects are on Intel/Samsung Foundry based on public information and analyst estimates.

• Intel Foundry

  • A NVDA 0.00%↑ GPU tile for the MediaTek Windows on ARM laptop chip in 2025. Built on Intel 3.

  • 5G ORAN basestation silicon for ERIC 0.00%↑ on Intel 4.

• Samsung Foundry

  • IBM mainframes (Telum, Z, Spyre) on SF5.

  • Various low-folume token projects from QCOM 0.00%↑.

    • Low-end 5G RedCap modems

    • Ultra low-end smartphone chips

    • Old smartphone chips re-branded for the IoT market)

  • A very small volume of Exynos 2400.

  • Groq and Tenstorrent because Samsung invested in them via convertible note. Round tripped revenue. (SF4X aka 4LPE PDK V2)

  • 1-2 large cap fabless semi players who will likely move consumer products to SF4X from TSMC N4P to free up TSMC wafer capacity for AI accelerators.

Only the last bullet point is serious volume.

Customers are proactively managing their booked TSMC capacity!

For those of you who are uncomfortable with investing in TSMC because of Taiwan invasion risk by PRC… are you invested in other semiconductor stocks?

If so, you should sell you semis. If TSMC undergoes an involuntary merger with SMIC, moderated by the CCP, the entire semiconductor industry dies overnight.

Geopolitics should not hold you back from investing in TSMC via the USA or Taiwanese listed shares.

I have high hopes for Intel 18A but it wont have any financial impact until H2 2026 at best.

Official Intel slide with Irrational Analysis crayon markings. Red is garbage. Yellow is really internal only. Lunar Lake is on TSMC N3B for a reason. Intel 3 node has poor power characteristics. Competing AMD and Qualcomm laptop chips built on TSMC N4P would crush a theoretical Lunar Lake on Intel 3 process tech. Green (18A) is the real money maker. Most of the existing capacity is for test wafers and Panther Lake until H2 2026.

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Broadcom is an excellent, well-diversified, well-managed business. Their IP portfolio is excellent and provides a huge technical moat for semi-custom (AI ASIC) silicon.

Harlan Sur's (JPM) Massive $AVGO Scoop

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I believe that semicap is a good long-term investment, but you should wait before adding or imitating a new position.

AMAT 0.00%↑, KLAC 0.00%↑, ONTO 0.00%↑, and CAMT 0.00%↑ are my favorites.

Onto and Camtek are somewhat insulated from the implosions of Intel Foundry and Samsung Foundry. TSMC CapEx spend will hopefully help keep them afloat.

I liquidated all the Applied Materials in my main account (~2/3) out of fear. The shares in my long-only accounts stay.

More bad news for semicap is coming. The consensus view on what is happening at Intel Foundry and Samsung Foundry is not accurate. Engineering reality is much worse. I believe all the ssemicap majors are at risk of a 10-30% further decline in stock price within the next six months.

TSMC negotiation leverage is a serious headwind for semicap that not enough people are talking about.

If you think I am wrong, invert me. Go buy the dip right now.

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I remain ultra bullish KEYS 0.00%↑. Low risk, medium reward.

Screaming Buy: $KEYS

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Finaly, I think that GEV 0.00%↑ is a great long-term investment. AI capacity buildout is going to place enormous strain on the USA power grid. GE Vernova makes giant natural gas turbines that provide good baseload power generation. Significant maintenance/service revenue too.

[4.b] Medium-Term (0.5-2 years)

Nvidia is tricky. I think that custom silicon from the Hyperscalers will out-grow Nvidia in the inference market as it develops. Nvidia is an excellent investment up until H2 2026. Don’t know what happens after that.

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Fabrinet and Vertiv are both winners of the AI buildout. The problem is their gross margins suck and they have a lot of competition.

I have traded in and out of Fabrinet and lost half my peak gains to news that Nvidia got a second source for 800G and 1.6T optical modal assembly. Maybe FN 0.00%↑ is worth buying but I have sold out at modest profit again to make my CIena position larger.

Researching VRT 0.00%↑ at the moment. It seems solid but I am not there yet. Liquid cooling, datacenter design, and electrical equipment. Great stuff, crap margins.

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Ciena is my favorite trade right now. Great products but horrible end market that is gona rip because of multi-datacenter training. More on CIEN 0.00%↑ in my upcoming optics post.

[4.c] High Risk

Shorting is intrinsically very dangerous. Infinite potential loss. Please do not short anything unless you really understand the mechanics and risk involved.

With that said, I am currently short ALAB 0.00%↑ and AMD 0.00%↑ to cover the void left by the old QCOM 0.00%↑ short.

Still think Qualcomm will be a nice funding short sometime in 2025, but for now the smartphone market looks great and my original thesis is invalidated.

AMD is overvalued from insane expectations for MI325X sales in 2025. Once Blackwell ramps, AMD DC GPU sales are gona tank. Willing to take on the risk for this one.

Astera Labs is comically overvalued. The sell-side notes that various subscribers have sent me are moronic. PCIe retimer revenue is going to plumet with the Blackwell transition. The narrative they have pushed on PCIe switches in utter nonsense. Only Amazon is going to use these PCIe switches because they are the only major customer not using Nvidia ConnectX cards (have integrated PCIe switch) for networking. Amazon also has a warrants (stock options) such that if they buy enough hardware from ALAB 0.00%↑, they get complimentary stock at a deep discount. These warrants are market distorting. It makes Astera Labs gross margins look much better than they actually are.

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As you can see from this chart, MU 0.00%↑ and SK Hynix are both partying at Samsung’s expense. Boomer PMs and value investors who bought into Samsung stock got rekt.

I am based out of the USA an access to Korean markets is limited. For those who have access, SK Hynix and Micron are both great high-risk investments. If Samsung continues to fail with HBM, both the competing memory stocks will double.

Previously made a lot of money on MU 0.00%↑ calls. Might trade back into this idea. Staying out for now.

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Marvell is a terrible long term investment. Broadcom is going to crush them over time. Fow now, 2025 call options on MRVL 0.00%↑ are an interesting high-risk, very high-reward tactical idea. Trainium 2 ramp is rumored to be hilarious. Totally unhinged.

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There are a lot of nuclear meme stocks right now. My favorite is LEU 0.00%↑. Bought in, somehow made 45% gain in less than a week and sold early. One more day of waiting would have made the gain ~85%.

So… what does Centrus Energy do? Nothing.

Here is a translation:

1. We have a special government license that allows us to buy uranium and act as a middle-man.

2. We have production capacity for a higher-enriched form of nuclear fuel (HALEU) that has zero commercial applications.

This abomination of a corporation is an extreme form of regulatory capture. Government dependence, the worst kind of dependence.

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Lumen is an abomination. Massive debt. Dogshit business model.

But look at this graph! LUMN 0.00%↑ builds fiber networks and signs long-term leases with customers. Multi-datacenter training has saved this shitco from the brink and they ended up adding more debt. After looking at how large my CIEN 0.00%↑ position has become, thought it would be fun to YOLO some of this year’s profits into this steaming pile of garbage.

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ARM is one of my favorite names, but it is low-float and high-risk. Qualcomm royalty revenue drop from V8 ISA Nuvia cores could be a surprise hit. Decided to take profit and liquidate the shares in my main account given the risky nature of my ALAB 0.00%↑ short.

Looking to buy back in later. Please don’t put more than 0.5-2% of your holdings into ARM 0.00%↑. Amazing investment, huge risk.