Harlan Sur's (JPM) Massive $AVGO Scoop
Incredibly Bullish.
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Let’s start with snippets from Harlan’s note.
This AVGO 0.00%↑ 3D SOIC modular reference platform is hyper-omega bullish. The engineering moat just got 100 meters deeper, and the sharks patrolling said moat now have laser eyes.
Key Investment Takeaways:
I believe Google’s efforts to move TPU projects to other (cheaper) vendors such as MediaTek ($2454.TW) and MRVL 0.00%↑ such got exponentially more difficult.
The recent addition of 1-2 custom-silicon customers is just the beginning.
Organic customer growth is almost certain.
Poaching design wins from competitors (Trainium/Inferentia from Marvell/Alchip) is now much more likely.
To understand why, you must understand the engineering behind 3D SOIC aka TSMC InFO_SoW.
TSMC InFO_SoW is very different from the CoWoS-S/R/L you may have heard about.
There is no substrate. This has massive benefits for both power delivery and signal integrity.
Drastically reduced packaging-related impedance at 100 MHz gives huge reductions of parasitic power loss from the power-delivery network.
When a chip takes in DC power of say 1.2V. the actual voltage is not flat 1.2V. There is always some ripple generated from a variety of factors, such as switching regulator speed and performance.
The reason TSMC quotes impedance reduction at 100 MHz is that directly correlates with how “good” of a power input the silicon sees. Reduces loss (better system power efficiency) and improves silicon performance (higher stable clock speed).
Next is insertion loss:
The 10-15% power saving claims by TSMC are nonsensical marketing hype. It is not possible to correlate insertion loss at Nyquist with interface power draw.
Still, the gains are quite nice. It would have been helpful to have a separate plot for 56 GHz (relevant for 224G SerDes) but we can assume 1-4 dB lower insertion loss depending on RDL trace length. Massive. Helps a lot with improving system performance for Ethernet, PCIe, and memory PHYs (HBM/DDR).
It is highly desirable for the insertion loss from 0 Hz to Nyquist (56 GHz in the case of the highest-speed interfaces) to be as linear as possible. Bumps and ripples cause problems for the receiver and must be corrected with expensive digital filtering, which adds meaningful power draw, reducing overall system efficiency (pj/bit).
Broadcom has developed an incredible platform on top of TSMC InFO_SoW with some of the deepest engineering moats ever seen in semiconductor.
Already industry-leading Ethernet, memory (HBM+DDR), PCIe, and NoC (network-on-chip) IP that has been ported and validated on InFO_SoW.
This is extremely difficult.
Setting up a modular platform like this will reap extraordinarily returns on investment as Broadcom has a decisive time-to-market advantage over competing custom-silicon providers.
Efficient use of engineering resources. (R&D OpEx)
InFo_SoW 3D platform allows the excellent Broadcom IP to perform even better with lower insertion loss (thus higher bit-error rate margin) and cleaner input power.
A proprietary chip-to-chip “MAX” interface IP that locks-out competitors from making lower-cost chiplets using the UCIe standard.
All the chiplets must be made by Broadcom, defending their content share.
UCIe is a mediocre specification. Whatever this “MAX” thing is, I am very confident is crushes UCIe in performance.
Harlan Sur of JP Morgan has reported on an incredible find. Credit to him and the JP Morgan team. They have missed how incredible this is from an engineering perspective.
It’s not just bullish, its omega bullish.