Coherent Lite Transceivers + AMD CPU Opportunity

Expanding on FundaAI's Excellent Work

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Extra Intro Note:

Thank you.

Never expected to make it this far.

100% of content will always be free. The pledge thing is for a theoretical future donation box. A backup in case my dumbass gets fired and blacklisted from industry.

But honestly, this…. hobby…. is now net positive for my career lol. Life it seems is stranger than fiction and some things going on behind the scenes. Don’t have to worry about being fired and unemployed anymore.

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Hello and welcome to a brief note on two completely unrelated topics. Recently read an excellent article by FundaAI on coherent lite transceivers. (not to be confused with the corporation named Coherent or the other corporation with ticker LITE…)

Deep|Coherent Lite Reshapes AI Optical Interconnects

Go sub to them. I am a paid sub on my real substack account.

One table bothered me….

EML having less area than a low-power CW laser is obviously wrong. Then there is the area issue. Photonic chips, particularly lasers and InP, tend to be narrow and long. So using area intensity is problematic. Need to use a wafer map calculator.

After spending half an hour running some quick sanity checks, I realized this table is completely wrong lol.

But Funda’s conclusions are mostly correct. Marvell biggest winner. Other investment conclusions also correct but InP intensity not as high as they think.

One core theme of the Funda piece is InP PIC for coherent lite. I can tell you that Tx will not be InP monolithic. Rx, there is nuance. I did some basic calculations on how much InP would be eaten if both Tx and Rx of coherent lite is monolithic InP and quickly realized this is crazy town. InP situation is already an unmitigated disaster. Adding this extra demand on top is like pouring all the stranded crude oil in the strait of Hormuz onto an existing InP dumpster fire.

Funda friends were kind enough to share the PDF of the Google paper (OFC 2026 tutorial) related to this topic.

https://x.com/phasentrpolator also sent me a great paper. Spent a couple hours flipping through textbooks and got enough material to work with.

Contents:

1. Coherent Component Crash Course

2. Google Paper Quick Overview

3. Summary of FundaAI’s Arguments

4. Wrong Parts

5. InP Yield and Area Crash Course

6. Irrational Analysis InP Intensity Model

7. Theoretical Optimal Coherent Lite Design

8. Winners and Losers

9. [Bonus] AMD CPU Opportunity

10. Trading Account Snapshot: 06/13/2026

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[1] Coherent Component Crash Course

I don’t want to bore you too much with how Coherent transceivers work. My primary objective is to teach you what the unique (compared to traditional IMDD) components are, why they exist, and how they affect system design.

If you understand the structures, you can easily understand the delta between coherent and coherent lite.

Fundamentally, coherent optics is the same as how wireless communication systems work. Data is encoded on two axis (I and Q), transmitted, and decoded later.

Another way of looking at this is as follows.

How to transmit complex numbers in the real world?

(use a sinusoid + 90 deg phase shifter to mix each channel)

The benefit of this strategy is a lot more bits per symbol. Wireless goes up to 1024QAM these days. Optics seems to stick with 16QAM.

In a previous life I worked on 1024QAM 5G/6G bullshit. Stupid feature. Tx EVM of commercial base stations cannot support unless ultra ideal conditions and even then not at max coderate.

Anyway, we know the benefit, so what is the drawback?

PHASE NOISE MANAGMENT

All components intrinsically have phase noise. Some more than others. Here is what your constellation looks like when phase noise is allowed to run amok.

You get a useless doughnut.

Phase noise problems are very difficult to debug and design around. Often the solution is “just use more expensive components bro”. Alternatively, people use complex (very area and power expensive) DSP (math) to characterize the phase noise of the system and back-out that transfer function in Rx EQ.

Always remember that engineering is all about tradeoffs. Understand these tradeoffs and you understand why people make design choices.

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Back to coherent optics, the LO in this case is a laser. The noise performance and polarization of the LO laser (ok every laser in a coherent system) is critical.

Laser linewidth is a measure of phase noise.

Phase noise is super bad in coherent systems, so the linewidth requirements are very strict. Easily < 0.2 MHz.

Managing phase noise, is painful. Trust me on this.

Leveraging symmetry is critical to removing LO noise. If both arms and photodetectors are precisely matched, large portions of the LO laser will be canceled out.

On the flipside if you screw this up everything becomes garbage and is unfixable.

RIN kills you.

Linewidth kills you much harder.

[2] Google Paper Quick Overview

Bottom (C) is a normal coherent transceiver architecture).

Top (A) is coherent lite.

Middle (B) is ugly, unnecessarily complex, and just worse than (A).

The fundamental delta between coherent and (polarization-folding) coherent lite is… polarization so let’s take a quick detour.

Polarization is the angle of light. Sunglasses work by filtering out some angles.

In optics, the nomenclature for polarization is TE and TM.

Broadly speaking, photonic structures (on Silicon, Silicon-Nitride, Indium-Phosphide, …) have one of three states:

1. Only accept TE mode.

2. Only accept TM mode.

3. Does not care about polarization.

For example here is a structure that rotates light from TM to TE.

And here is a structure that separates TE and TM modes.

Broadly speaking, dealing with polarization on SiPho is much more annoying than InP…

… at the cost of area. Remember, tradeoffs.

Now let me annotate the Google coherent lite block diagram to help you understand why it represents beautiful engineering (good tradeoffs).

Notice how nothing in the Tx block diagram involves polarization. This is a good thing!

Massive cost-down enabled by SiPho PIC.

The key to understanding coherent lite is polarization-folding.

Why go to the trouble?

The answer is surprisingly simple.

The transmitter output it going to have random polarization. If you get unlucky, the receiver will get very little light because most of the light is on the wrong polarization/mode.

The entire receiver in coherent lite is designed around a specific polarization (prob TE). We cannot afford to waste light/energy trapped in TM mode.

Very clever trick. Dramatically reduces complexity and cost on Rx.

The DSP needs to do some extra math though. Intuitively, the transfer function of the polarization folding unit is 1 + Z^-1. Dug up the partial response signaling paper out of curiosity…

Yea this is straightforward. Use all energy, force it to be on TE mode, and have the DSP back out a simple transfer function before running anything else.

[3] Summary of FundaAI’s Arguments

1. Coherent lite is going to be huge because of Google.

2. Driven by OCS insertion loss budget.

This is correct although 3 dB loss on MEMS OCS sounds high. Wonder what size of OCS switch induces such loss.

[4] Wrong Parts

Now for the wrong parts.

This is completely wrong. Transmit is not more complex. Line rate for each MZI drops to 168Gbps. SiPho already works at 224Gbps line rate.

168 is in fact a smaller number than 224.

Nothing in the transmit side is polarization sensitive. There is no need to use InP. SiPho will do just fine.

(Tower Semi sipho, not that GloFo dogshit)

A MZI modulator can easily hit 5 mm long. Using InP for coherent lite Tx PIC would obliterate the industry. Also would obliterate cost.

I will come back to the estimates. Entire FundaAI table is wrong as a reminder. I’m not kidding or trying to be mean. All the numbers are wrong.

[5] InP Yield and Area Crash Course

Indium-Phosphide is a satanic nightmare. As a ballpark, yield of 50% is considered normal for discrete devices (CW laser, EML).

Unlike silicon/logic, there are no tuning parameters to harvest parametric issues.

Some of your InP devices will be at the wrong wavelength. Too far away from target to thermally tune via TEC. You fucked.

Some InP devices won’t hit target power at target temperature (typically 40C or 50C). Nothing to be done.

Some InP devices will be flaky, exhibiting erratic behavior at target setpoint. This is called mode hopping. Can’t do anything. YAY INDIUM PHOSPHIDE IS AWESOME.

Also InP is a very brittle material. Lots of dice die as you try to package and wirebond.

[6] Irrational Analysis InP Intensity Model

I have build a model using numbers pulled from my anus. Maybe I know things. Maybe I don’t. Wink wink.

[7] Theoretical Optimal Coherent Lite Design

It is unclear to me what the actual architecture will be but here are my best guesses. The design space is pretty open.

1. Tx

   1. DFB (no ITLA)

   2. Tower Sipho with MZI modulators.

   3. Each modulator signaled at 168Gbps.

   4. Marvell or Semtech Drivers

2. Rx

   1. Monolithic InP PIC (Coherent the corporation or Nokia)

   2. TIA from Marvell or Semtech.

3. DSP

   1. This is Marvell.

   2. 8x 336G PAM6 SerDes receive from host

   3. 16x 168G PAM4 SerDes to PIC

[8] Winners and Losers

Marvell is the biggest winner by far. They gona make so much money on the DSP and have great driver/TIA bundling oppertunities.

Tower wins because more sipho and GloFo is actually incompetent.

Semtech win but maybe not as much as I hope. Marvell might take most of the sockets inside the transceiver.

Macom lose because photodiodes integrate into InP PIC.

Coherent (the corporation) and Nokia win with 6in InP process for monolithic InP PIC. Other InP players won’t want to burn their 4in capacity on this.

[9] [Bonus] AMD CPU Opportunity

Suppose AMD gets more wafers from TSMC. Assume this but don’t think about it, unless you were on the recent Raymond James bus tour.

Thos incremental N3P wafers would all go to datacenter CPU, the hottest and by far highest gross margin product line AMD has.

Been chatting with some contacts and I don’t think any of them understand the money tsunami Dr. Lisa Su is capable of unleashing IF AND ONLY IF SHE GOT MORE N3P WAFERS.

AMD Turin uses N3P for the CPU core chiplets and N6 for the I/O die.

By far the best implementation of chiplets. Their numbers are dirty. Let me show you.

[10] Trading Account Snapshot: 06/13/2026