Thanksgiving Thoughts: TPU VS NVDA, AVGO, MediaTek, Intel Foundry
Irrational Analysis is heavily invested in the semiconductor industry.
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Contents:
Google/TPU vs Nvidia/GPU (a retarded discourse)
Continued Bullshit on MediaTek TPU: Contcat FEC Edition
Intel Foundry: Packaging is Key
Trading Account Updated Disclosure
[1] Google/TPU vs Nvidia/GPU (a retarded discourse)
Nothin from the engineering side has changed.
But the vibes have shifted… to a much stupider regime.
Within my LONG ONLY accounts, NVDA 0.00%↑ is still largest position.
But my trading account has zero exposure to Nvidia.
If it hits $160, I buy some calls. Probably 200/220c 6 months out expiry.
If it hits $150, I double down.
Sometimes, trading is not about being right.
It’s about realizing when many people are wrong and engage in stupidity echo chamber.
[2] Continued Bullshit on MediaTek TPU: Contcat FEC Edition
This summer, an amusing number of buyside (professional investor) people repeatedly asked me about my thought on Google moving huge volumes of TPU from Broadcom to MediaTek.
Legit was running a private group therapy program for bunch of dudes who collectedly managed $20B+ worth of AVGO 0.00%↑ stock lol.
I turned out to be right. MediaTek TPU got delayed multiple times and volume slashed from what Taiwan rumor mill was putting out.
A basic understanding of how burst errors effect high-speed SerDes would lead you to the same conclusion.
Now, the Taiwan rumor mill is re-cycling the same shit.
MY OPINION HAS NOT CHANGED.
To understand why, let’s look at a 2024 paper on FEC strategies presented by a galaxy-brain Broadcom employee.
Taiwan rumor mill incorrectly assumed the following logic:
Broadcom wont implement thing Google wants.
MediaTek will implement thing.
Huge volume shift of TPU from Broadcom to MediaTek!!!!!
“Inner-outer” FEC is the keyword.
In a particular group call with a bunch of western buyside guys, the networking expert analyst brought up this keyword while we were discussing Googles relationship with Lumentum and Marvell.
This guy knew that Marvell implemented “Inner-outer” FEC in their optical DSP and that would result in a Lumentum keeping high Marvell share over switching to Broadcom DSP.
Like the Taiwan rumor mill gremlins, he knew the keyword but did not understand what it means.
Let’s go over the paper.
The correct term for “inner-outer” FEC is concatenated FEC.
Concatenated error correction code - Wikipedia
FEC means forward-error correction.
By adding some extra bits to a packet, you can use fancy math to automatically detect and correct a certain number of errors.
Reed-Solomon(544,514) is the most popular FEC scheme in high-speed wireline communication systems. This is the default.
It can correct up to 15 errors per packet.
However, in the age of AI, latency has become critical so all hyperscalers want to run half RS-FEC.
In practice, this means the performance bar suddenly went up and caught SerDes world off-gaurd.
Now, you can only have 8 errors per packet. In practice, you need margin so < 5 errors per packet is the real target for qualification.
Let’s look at Broadcom persons analysis for alternative RS-FEC setups.
Ok so the default (544,414) is the best option still.
Anything else either kills latency or requires higher SNR.
802.3dj is the IEEE spec for 200G per lane Ethernet SerDes.
Now lets look at the first plot. There are gona be a lot of these.
Here is how to read these plots:
X-axis is the signal-to-noise (SNR) ratio.
Y-axis is the post-FEC bit-error-rate (BER)
The dashed horizontal line is spec target.
Your goal is to hit this horizontal line with the lowest SNR possible.
Less SNR needed to meet spec means more margin for the system.
In this first simulation, you can see the black line is best.
This is because black line is modeling purely random errors.
The other lines have various burst error models.
Burst errors kill real-world performance.
Traditional RS-FEC is designed to handle burst errors well, at the cost of latency.
Now here are two scenarios where concat FEC would make sense:
[1] You have an optical transceiver channel where the electrical portion is prone to burst errors but the optical portion only has minor random errors.
OR
[2] Hock Tan has you in a chokehold, every fucking SerDes vendor has failed to meet your spec, but the nice MediaTek people might be able slightly improve their sub-standard SerDes by blowing up digital logic area to implement concat FEC.
At a high-level, Taiwan rumor mill latched onto option #2 without understanding where burst errors come from, why concat FEC does not help with burst errors, and the underlying reasons why Broadcom and IEEE standards bodies shut Google’s stupid proposals down.
The 26-page Broadcom paper has the answers to all of these questions!
Let us continue.
Compare yellow line (normal RS-FEC) with purple line (concat FEC with hard decision). Way better!
But notice that no burst errors are in above simulation.
Soft-decision concat FEC is even better!
But notice that no burst errors are in above simulation.
Once you add back in burst error modeling from DFE error propagation (h1), the gaps narrows quite a bit.
Dark blue (baseline RS-FEC) and dark red (concat FEC with high burst errors) not that different. Only a ~0.8 dB SNR delta.
DFE means decision-feedback equalizer.
All modern high-speed SerDes use a single DFE tap.
Except MediaTek’s.
MediaTek SerDes made design decisions that make them FAR MORE VUNURABLE to burst errors from DFE taps.
Partially this is to deal with the hell of adding gain into their ADC interleaves lol.
This kind of tradeoff is fine if you are willing to calibrate to a specific channel. But for dealing with complex situations, lol NO.
Key Points:
Assuming MediaTek has not completely re-done their 200G SerDes design (removed second DFE tap, remove gain in ADC interleaves), they are very prone to burst errors and not competitive with Broadcom for primary TPU socket.
I can see MediaTek getting some volume for a small prefill-optimized TPU.
Simple PCB channel with low reflections.
Package design simple and allows for routing margin.
Broadcom is safu.
[3] Intel Foundry: Packaging is Key
TSMC is smart. They build advanced fabs in Arizona/USA but zero advanced packaging capacity.
All the chips need to be shipped back to Taiwan to be packaged.
Intel Foundry’s major foot in the door was always advanced packaging IMO.
Unfortunately, self-inflicted stupidity delayed the ramp by like 2 years. 🤡
Thankfully, Lip-Bu Tan is cleaning house and poached a competent TSMC executive.
Taiwan is raiding this dudes house over trade secrets theft bullshit because they know the jig is up.
TSMC refusing to build advanced packaging capacity outside of Taiwan was clever and the idiots in USA government fell for the song and dance in Arizon.
But now, Intel has removed head from ass and is ready to deploy EMIB at scale.
And before some semicap nerd emails me on how EMIB and CoWoS-L are SO DIFFERNT. Fuck off.
From a design and signal integrity perspective, these two technologies are effectively the same.
On an 18AP front, we got the first low-priority order today.
Rubin gaming should be next.
[4] Trading Account Updated Disclosure
I have withdrawn (finally) all the money needed to pre-pay my outstanding tax liabilities. Also that retarded WPE bet I made with Doug.
The INTC 0.00%↑ calls shall be held until assignment. I’m not trimming until Intel trades at least 2x the P/B of GFS 0.00%↑.
I am waiting for wash sale period to pass before buying back into SITM 0.00%↑ and BE 0.00%↑.
Have a huge writeup for end of the year on like 30+ obscure/dangerous ideas.
Hey, just wanted to pen a Thanksgiving thanks for writing all these articles and sharing your thoughts with us.
I thought Amkor is building in Arizona to be the preferred advance packaging partner for TSMC?