OCP Global Summit 2025: Irrational Recap

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Messa back with moar conference coverage.

I will group most of the material by theme.

Contents:

1. Theme: Co-Packaged Optics

2. Theme: 400G Electrical SerDes

3. Theme: Optical Transceivers

4. Theme: Scale-Up Protocols, ESUN, and UALink Death

5. Miscellaneous

   1. Marvell Alaska AEC

   2. Bloom Energy

   3. QLC Storage

   4. Cool Cable Length Measurment

   5. Multilane Test Equipment

   6. Interesting 3D Etched? Copper Coldplates

   7. Point2

   8. Elyian

6. Funny Shit

7. Public-Market Investment Corner

   1. Updated Disclosures and Holdings

   2. Opinion by Ticker

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[1] Theme: Co-Packaged Optics

CPO was huge at OCP. Easily 10+ dedicated talks just on this topic.

Quick high-level summary by company…

Broadcom AVGO 0.00%↑ showed incredible data from reliability, performance, and power fronts. Really incredible stuff. They also showed interesting VCSEL based CPO.

Nvidia NVDA 0.00%↑ did not show anything new. All material was already presented at GTC and Hot Chips earlier in the year. Complete waste of time.

Accelink $002281.SZ hard a lot of nice presentations. Impressive ELSFP output power for CPO.

Marvell MRVL 0.00%↑ showed literally zero data. Some nice block diagrams though.

Ciena CIEN 0.00%↑ (Nubis recent acquisition) had an interesting take on DWDM that I strongly disagree with but respect.

* Note: Withholding coverage of micro-LED for an upcoming photonics post. I hate micro-LED with the fire of a thousand suns. Will explain later.

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Many people within industry complain that CPO has worse reliability than transceivers. These people are idiots who have no idea what the hell they talking about. Broadcom showed excellent reliability data that should have put this debate to rest. Unfortunately, stupidity is often difficult to stamp out.

Case in point, this idiot who replied to one of my tweets.

As a baseline, here are the most common failure modes for traditional pluggable transceivers.

It’s the laser and wirebond/packaging that kills these things.

This is what wirebonds look like:

These things look fragile because they are.

CPO does not use any wirebonds. COUPE and RDL-based CPO methods are zero-wirebond.

Next, let’s talk about PCB mounted component errors.

In general, the most unreliable sub-components are Germanium-based photodiodes (ger-PD).

Think of ger-PDs as a necessary evil. Every optical system (transceiver, CPO, whatever) needs these things.

Germanium PDs are….

1. Much higher failure rate than any other photonic structure.

2. Very sensitive to ESD.

3. Can degrade over time if you are stupid and botch basic design principals.

Here are examples of germanium PD in traditional transceivers…

In general, integrating all germanium PDs into a single SiPho chip greatly reduces the probability of failure over time. Every single PD is tested at wafer level, greatly improving economics. Finally, discrete or partially integrated PDs can be damaged in handling and packaging. Fully integrated PDs within a SiPHo chip are much easier to protect during manufacturing/assembly.

Nearly all CPO implementations use integrated PDs and thus have significantly better reliability in this regard.

Next, we have lasers, the most unreliable component of any optical system. I have a lot more material sitting in my drafts folder so here is a quick summary:

• Lasers are made of III-V material, typically Indium Phosphide (InP).

  • Shit yield.

  • Shit reliability.

• Laser diodes are very sensitive to temperature.

  • I am talking +/- 0.1C sensitive in some cases.

  • Often, it is desirable to keep a laser at a specific temperature to ensure no mode hops (jumps in frequency response) and better efficiency.

• All lasers degrade over time (lower power over time) and need to be burned-in and margined appropriately.

• Charge density is the main factor for degradation.

All CPO systems use external lasers (ELSFP) that are intrinsically much more reliable than integrated lasers within transceivers.

This is because temperature can be controlled much more easily and a fewer number of higher power lasers (with larger die size to keep charge density the same) are needed. Fewer points of failure… and PLUGGABLE ANYWAY IN CASE OF FAILURE.

CPO (when done right) is intrinsically more reliable than traditional optical transceivers.

Case in point… Broadcom.

This is incredible long-term FEC data. Not a single FEC bin above symbol 12.

In fact, if people were willing to tolerate a very small amount of packet drops, half FEC (8 bits) could be used.

Incredible power savings.

Massive improvement in mean-time-between-failure.

Broadcom actually got ZERO FAILURES in this 1M device hours of data. They need more data to claim higher MTBF. It is currently unknown how good Broadcom CPO really is. The 2.5-million-hour MTBF number is simply the statistically best they can claim with existing PERFECT data.

Zero is perfect track record. What the hell are you smoking, CPO reliability bears?

🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡🤡

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In contrast to Broadcom, Marvell showed literally zero data.

I attended the Marvell CPO talk and there was zero data. Just some block diagrams.

I asked at least four people at the Marvell booth if they could disclose any information similar to what Broadcom has shown repeatedly over the past year.

• pre-FEC BER.

• FEC tail

• MTBF

• Power consumption vs transceiver.

Literally nothing.

System looks cool but there is no public evidence all lanes can operate while meeting FEC requirements.

Here is the data Broadcom showed over a year ago at Hot Chips 2024.

Looking forward to public data from Marvell on their CPO solution.

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Next, lets talk about Nubis (now part of Ciena CIEN 0.00%↑) CPO presentation.

Ciena/Nubis presenter argues the following:

• CPO should use high-speed (200G —> 400G) SerDes.

• Single-wavelength is enough.

• Scaling should be via large fiber arrays and grating couplers.

I strongly disagree with these arguments for a variety of reasons:

• D2D clock-forwarded SerDes (UCIe, NVLink D2D, Broadcom MAX, Marvell 64G D2D, Elyian, …) has far better shoreline density and energy efficiency per bit.

• Every fiber attach is a point of failure.

• More fiber attachments reduce yield.

• Grating coupler alignment is very challenging to scale.

• DWDM based scaling, driven by D2D NRZ clock-forwarded SerDes is the optimal solution for co-packaged optics.

• Laser power requirements grow exponentially as datarate and modulation scheme go up. (to maintain SNR/BER targets)

Engineering is about tradeoffs and strategically choosing which problems to solve.

Ciena/Nubis presenter argues for the opposite of my personal beliefs, but I respect his stance because there is logic behind it.

Still strongly disagree.

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Accelink had some nice CPO material and demos, particularly on the laser side.

The NPO solution is a scaled-up SiPho chip. Same (or at least very similar) MZI modulator system they use in transceivers.

Moar content for TSEM 0.00%↑ huehuehuehue.

Pretty good results but the curve looks too smooth. Perhaps they only used one device to generate this data?

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Now for the really good Accelink stuff… ultra high-power ELSFP.

Excellent optical power and stability. Really kickass data.

Efficiency is a bit low to be honest. But the power flatness is so incredible that efficiency gap does not matter IMO.

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Broadcom also showed VCSEL CPO driving each laser with 100G SerDes.

This is an interesting niche solution. Cannot scale past 100G but really good at that speed.

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Lumentum presentation trying to shill thin-film lithium-niobate.

I don’t know enough about material science to comment. People tell me that TFLN is very far out.

Lumentum has higher content with InP based modulation solutions. There is a reason they are throwing shade on SiPho.

[2] Theme: 400G Electrical SerDes

I have strong opinions about PAM4 400G electrical SerDes.

Systems people look at unreasonably optimistic channel models in pretty MATLAB simulations while handwringing over SNR requirements of PAM8/6.

Myself, and anyone else who has measured real channels with a network analyzer, knows that real channels are shit and PAM4 400G is not going to work for most channels.

So your reference channel is shit after 85 GHz but you still arguing for Nyquist well over 85 GHz. Nice.

COM simulations are already bullshit.

Not including crosstalk in the simulation makes it extra bullshit. LOL

Only way 400G PAM4 SerDes works is if you use exotic channels like co-packaged copper.

Here is the Ciena connector for telco transceivers.

And some more notable connectors.

Samtech somehow managed to make a magic connector. This shit is mind-blowingly good.

Anyway, PAM4 400G is a dumb idea that should not be standardized. It is too risky to limit official standards to niche CPC channels.

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Ciena’s 400G SerDes is kickass but they have a rather glaring issue that needs to be fixed. Can you spot it?

There is a random noise problem. Look between the symbol histograms.

There is a floor. Not good.

Many possible root causes but one guess would be poor ADC interleave calibration.

Ciena needs to fix this. Given how great the rest of their data is, I’m sure they will figure this out.

[3] Theme: Optical Transceivers

While CPO was super popular, transceivers are not going anywhere. See this Lightcounting data.

I am much more bullish on CPO than Lightcounting. Think CPO market share is much higher in 2029 onwards.

But regardless, CPO is not a universal solution. Transceivers will always have a place in the market.

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Let’s start with the holy war against DSP chips.

Everyone wants to remove the DSP because of two main reasons:

1. Huge BOM cost contribution.

2. Large power consumption contribution.

LRO is a silly half-measure in my opinion.

LPO is the way forward, and it can work great if done right.

Channel variation across switch ports is a major issue that needs careful tuning and optical module design to overcome.

Some CTLE, driver, TIA, linear EQ configuration (Semtech, Macom, Marvell) is needed to account for such variation.

Mildly annoyed Accelink did not show FEC tails but whatever.

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Credo has a 1.6T optical DSP now. Heard rumors it was good (perf and power consumption) and rumors were confirmed at the show.

Pre-FEC BER is good. Matches Marvell.

TDECQ is decent. In general, sub 1.5 dB is the target.

They are using a low-noise laboratory-grade laser though. Sneaky sneaky.

Next, lets go over Credo’s “zero flap” OCP proposed standard.

It’s mostly laser mode hops due to thermal drift but whatever go on…

Credo has developed a nice tool/firmware framework for monitoring optics. They will also donate this work to OCP.

Nice. Kudos.

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Let’s go over OCP NIC standards updates. The optical modules need to plug into something on the host end.

The answer is yes. Please kill Astera Labs.

Good. Artificial power limits from standards bodies have been harming NIC innovation.

Astera Labs probably has the following feedback for 64x-PCIe lane OCP NIC standard.

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Finally, lets talk about Marvell’s 1.6T optical DSP.

Three people at the conference told me that Marvell is out from Nvidia transceivers. All three said that Nvidia would dual-source between their internal DSP and Broadcom’s.

When I asked why Nvidia would go to the trouble of dual sourcing the DSP, I did not get very credible answers. If people want supply-chain resilience, they will go buy non-Nvidia transceivers from Innolight, Accelink, Eoptolink, Lumentum, Coherent, or several other players.

How the hell is buying a Broadcom-DSP powered Nvidia transceiver of any strategic value to end customers?

Marvell had a demo of this DSP chip and it is basically useless.

Oh wow FEC symbol 2. What is the test setup?

Only the optical-side SerDes is active and it’s in a synchronous (zero PPM) loopback on a simple 4-5 dB copper channel.

Maybe Marvell was afraid of the Barclays gremlin showing up and nitpicking their optical DSP over 1 watt again.

Regardless, I am tired of trying to figure out if Marvell is in or out of Nvidia 1.6T transceiver.

Look at this graph.

• 800G transceivers going to the moon.

• Nobody is going to bother designing Marvell out of that generation.

• Yes, massive share loss in 1.6T generation.

  • So what?

  • Marvell/InPhi gona massively grow.

• If you are looking for a Marvell short thesis, this isn’t it.

  • Idiots who still expect Maia program to ramp up is why you might want to short Marvell.

[4] Theme: Scale-Up Protocols, ESUN, and UALink Death

ALAB 0.00%↑ stock tanked because of OCP announcements.

Notice who is not on the ESUN supporters list?

<whispers… ALAB…>

UALink was already dead but now this joke of a standard is extra dead. The body has been burned and the ashes dissolved in hydrofluoric acid for good measure.

Here is a rough timeline of what happened in standards politics land.

1. UALink was formed when AMD donated their specification to the org.

2. Broadcom joined, realized they were the only ones who had a viable SerDes, and left.

3. Broadcom made SUE.

4. Meta (and presumably other hyperscalers) panicked and negotiated for Broadcom to re-join the fold… by creating ESUN.

At a high level, ESUN exists to standardize the switch-side digital bits, while leaving client-side digital bits open to customization.

As a starting point, Broadcom SUE has been donated as a default client-side protocol.

https://www.opencompute.org/wiki/Networking/ESUN

https://www.opencompute.org/w/index.php?title=Networking/SUE-T

Two companies were pro-UALink (from the purchaser side of the equation): Amazon and AMD.

Amazon has dual-tracked Trainium 4. There is an NVLink Fusion version and a UALink version.

AMD has also dual-tracked their GPU program. There is a UALink version and an ESUN version.

I believe both Amazon and AMD will abandon UALink.

This is really bad for Astera Labs as their switching content will be replaced by Nvidia and Broadcom respectively.

Proud member of a dead standard replaced by the open OCP endorsed ESUN protocol.

Astera Labs had a meme rack on a rotating display trying to claim they are the open standard scale-up leader. Kept talking about PCIe-based scaleup with retimers on every link.

LOL

Broadcom, Nvidia, Marvell, NextHop, and Upscale are going to vaporize these fools.

[5] Miscellaneous

Random interesting things that don’t fit into any broader theme.

[5.a] Marvell Alaska AEC

Marvell’s AEC DSP is incredible. Supports up to 9 meters of length.

Look at this FEC histogram! (7 meter version)

This is amazing. FEC symbol 4.

Obviously, some favorable (aggressive) active cooling was used for this demo.

Regardless, this demo is so good that it is reasonable to assume that half-FEC operation (half latency) is easily achievable with Marvell Alasca AEC.

I asked the Marvell people why Credo is getting away with highway robbery given that Marvell has a superior product in terms of reach, performance, latency, and power.

They said some excuses like… oh no Credo is vertically integrated and we only sell the chip and we have lots of partners and don’t want to compete with them to take content blah blah blah.

So what?

Design the stupid PCB yourself and give it to each partner for free. Accelerate your time to market.

Credo’s margins are your opportunity!

Stop giving me lame excuses and go kill Credo.

I pitched long MRVL 0.00%↑ short CRDO 0.00%↑ to every finance person I met up with at OCP and this trade got shot down by every single one of them.

Credo ramp so big oh no messa scared to short this overvalued meme stock.

[5.b] Bloom Energy

Bloom energy has a time-to-power advantage.

The tech is mediocre in basically every other way. Only real advantage is you get datacenter powered up faster.

This alone is enough for considering going long BE 0.00%↑ but given how I missed the rally, been sitting out.

Then I see this…

Supercapacitors to improve transient ripple for 800V DC direct supply?

Configurable and modular reliability scaling?

I bought some shares. Need to do more research before sizing up the position.

[5.c] QLC Storage

Meta is deploying QLC flash storage at scale.

Power and density important.

Shilling Purestorage. (this shall be short lived)

Ah so you are in the process of designing out Purestraoge. Nice.

Slide complains about CPUs taking too much power budget. Need to move to next-gen manycore x86 CPU single-socket platform.

The presenter was very… vocal about how much he hates the Intel Saphire Rapids dual-socket power draw. Man was genuinely pissed.

So Meta is either going to use AMD Venice Dense or Intel Clearwater Forrest.

(probably AMD but we shall see… not material to either AMD or Intel stock)

ARM solutions unlikely because Meta seems concerned about CPU core performance in this application.

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NAND flash naturally wears out over time.

Overprovisioning is a process where a portion of the total raw storage capacity is set aside for future use.

So your “1 TB” SSD might actually have 1.1 TB of raw capacity for example.

All flash storage devices use this tactic but with varying overprovisioning ratios. Electric cars also overprovision batteries.

Anyway, due to some complicated underlying nuances, the overprovisioning needs to be spread out.

Very cool.

[5.d] Cool Cable Length Measurment

Meta has developed a neat software tool that can measure the cable length of any run inside a multi-datacenter network. Inside and outside the datacenter.

Very clever distance approximation. Commercial wireless world has used similar tactics since 2018. Delay-based distance estimation is a common military signal-processing challenge.

The most difficult part of what Meta’s system is estimating the switch latency itself. They seem to have collected a small dataset of known-length runs to calibrate out the unique delay of each switch model.

Meta claims to have accuracy of within +/- 10 meters. Really incredible stuff.

[5.e] Multilane Test Equipment

A small privately held test equipment company you probably have never heard of had a meaningful impact on improving the yields of complex AI scale-up cabled backplanes.

The original way these backplanes were tested is via optical inspection and basic continuity tests. (probe pins with a multimeter lol)

No measurement of signal integrity, BER, s-parameters, or TDR pulses.

This strategy did not go well.

The reason nobody was testing these backplanes properly was the equipment to test so many differential pairs at the same time did not exist.

When backplane (rack-integrator) yields were at < 10%, everyone was playing a fun finger-pointing game.

• This is Amphenol’s fault.

• No no no it’s FIT/Wistron/Quanta/… fault.

• No no no the customer does not know how to operate advanced AI racks…

• No no no the design itself is too complicated and cannot be manufactured at scale.

Multilane helped the ecosystem dramatically improve yields (80-90%) by creating a giant 64-lane BERT (bit-error-rate-tester) that can slot entire sections of a backplane in for one giant test.

• Real hardware FEC BER measurements.

• Real channel impulse response.

• Real SNR calculations.

• Real insertion and return loss.

To give some context, a high-speed BERT capable of testing ONE DIFFERNTIAL PAIR at 200Gbps speeds costs around $700K minimum.

Buying and wiring up 64x $700K boxes is stupid and unviable. There is a reason the ecosystem took the lame way out (basic continuity tests and optical inspection) and ate shit shortly thereafter.

Multilane found an incredible niche and are serving that market INCREDIBLY well. It’s kinda crazy. I am very familiar with the traditional electrical test equipment market. Keysight, R&S, Tektronix, Anritsu, Spirent, Teledyne, RIGOL, …

Nobody else has what Multilane can offer. The sheer value these guys deliver is crazy.

[5.f] Interesting 3D Etched? Copper Coldplates

Some Chinese company I never heard of made these.

Held few of these in my hand. They are super solid and sturdy. It’s looks like a deepfake but it’s actually real.

Somehow they use lasers to print these weird shapes.

Super interesting.

[5.g] Point2

Interesting mmWave over plastic tube high-speed connectivity.

Vikram Sekar has a great writeup.

Plastic Cables for AI Clusters: Can Point2’s E-Tube Disrupt Copper and Optics?

Wow these numbers look great for 200G per lane.

Let’s see the eye diagram.

Oh you only have a live demo for the 100G per lane version? Ok let’s see it.

That is a decisively “mid” eye diagram.

Credit to them for actually showing this publicly.

(looking at you Marvell CPO department showing literally zero data)

Hope Point2 makes improvements and brings 200G per lane product to market. Tech is really cool and wish them the best of luck.

[5.h] Elyian

It looks great.

Bi-di electrical SerDes works using a precise analog circuit that uses phase shifters to subtract out the local Tx from the Rx.

Nvidia has a nice paper on it.

https://research.nvidia.com/publication/2022-06_0297-pjbit-504-gbswire-inverter-based-short-reach-simultaneous-bidirectional

Marvell has a 64G D2D PHY that is conceptually very similar to both Nvidia and Elyian’s solutions.

Properly calibrating and controlling all these phase shifters is challenging.

This is pretty good. Marvell claims higher BW/mm but they need expensive advanced packaging.

To the best of my knowledge, Elyian’s claim of having industry leading density on standard package is correct.

Eye diagrams look great.

Excited to see these guys get design wins.

[6] Funny Shit

AMD had a marketing own-goal at OCP.

Proudly on display was the Helios AI rack.

But if you look closer… there are… other hardware vendors in this rack.

That’s right… Nvidia 800G optical transceivers.

A hedge fund friend pointed this out to me when I met him. Couldn’t believe it. Went back to the show floor to see for myself. Tweeted out the pictures and it blew up way too much.

Apparently sell-side analysts were congregating in the Hillton hotel lobby trying to decipher what this means.

Someone emailed me that pod monkeys were bidding up Fabrinet FN 0.00%↑ because of my joke tweet.

What the fuck are you clowns doing?

Look at the transceiver manufacturing dates.

September 2022

Transceivers over 3 years old.

Realistically, here is the most likely chain of events.

1. AMD needs to put together a non-functional rack for the show floor.

2. They need transceivers to complete the rack.

3. Someone at AMD makes the **hilarious** mistake of using old Nvidia transceivers from 2022 that were originally purchased for competitive analysis and have been collecting dust for years.

This fiasco has zero engineering, investment, or strategic implications.

It is hilarious. That’s it.

AMD removed all the transceivers the day after my tweet.

To all the tourists who commented saying “Nvidia bought Mellanox” and “Nvidia networking is good and companies do business with each other all the time.”

Nvidia bought Mellanox in 2019.

There are at least 6 large and reputable 800G transceiver vendors AMD could have used for their NON FUNCTIONAL SHOWFLOOR DEMO RACK.

1. Lumentum

2. Coherent

3. Accelink

4. Innolight

5. Eoptolink

6. Cisco

All AMD had to do was ask a hyperscaler for a bucket of dead NON-NVIDIA transceivers for their Helios rack demo.

There is no way in hell AMD would ever use Nvidia transceivers in production.

This is a hilarious marketing own-goal. Nothing more.

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Keynotes and food service were held in a separate nearby building.

A literal Meta GPU tent.

LOL

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Bloom Energy presenter spent 3 minutes giving a weird story about a rabbit riding a tortoise. I timed him.

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Finally, we have this slide, which wins the award for “most useless slide of the conference”.

Completely unreadable lol.

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[7] Public-Market Investment Corner

Shame on any pod monkeys who skipped direct to this section.

[7.a] Updated Disclosures and Holdings

Reminder that trading account and long-only accounts are disclosed separately because updating manual spreadsheet is painful.

Long Only:

Trading:

[7.b] Opinion by Ticker