Micron FQ4 2025: MEETHINKS YOUSSA DOTH PROTEST TOO MUCH
HBM4 Base Die Cope --> Obvious Bullshit
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Allright the Micron earnings call and call-back are quite interesting from an engineering perspective.
I see an opportunity to inject some chaos into the conversation.
This is gona be real fun. 😈
First, biases.
I have frankly botched trading Micron this year. Very poor track record given the insane risk exposure.
Had some small degen options positions and liquidated them all before earnings. Good move TBH given the hilarious IV crush.
The chart is terrifying.
And so is the price/book ratio.
If you are valuing the “black-tar heroin of semiconductor investing” on forward P/E, you are an idiot and deserve to lose money.
I have zero intention to touch Micron stock or options. This shit is scary. Have a good YTD P&L to protect. Not gona blow this trying to 5-head a memory cycle riddled with landmines. There are plenty of easier ways to make money that require less brain damage.
Genuinly have NO IDEA what to make of Micron.
Long, short, calls, puts, no fucking clue.
What I do know is that their commentary on HBM4 11 Gbps per pin is complete bullshit. They made a bad decision and in blew up in their face.
Stock could still go up anyway. Traditional DRAM shortage and demand cycle could save them from getting locked-out of HBM4 and waiting for HBM4E.
My official rating is:
¯\_(ツ)_/¯
Contents:
Background Rumors (before the earnings call)
Earnings Call
Callback (second call to feed sell-side more bullshit)
Memory-based Logic HBM Base Die
Parametric Yield Crash Course
Interrogation Guide for Financial Professionals
[1] Background Rumors (before the earnings call)
Around one month ago, rumors started circulating about Micron’s HBM4.
Apparently, Nvidia raised the speed requirement to 11 Gbps per pin, well above official JEDEC spec of 8 Gbps.
Allegedly, Nvidia asked for 10, then raised the bar to 11. SK Hynix delivered, Samsung is contested (some say they dead, others tell me they qualified), and Micron got fucked.
Semianalysis was first to report this. I know because 3 core research clients pinged me and two people who I know don’t have core research pinged me too.
I pinged one of the people who takes pictures SA notes on my behalf to see for myself what the hubuhb was about.
Basically, the only information that matters to me (in the note) is that Micron idiotically decided to use their own internal logic node (based on memory process node) for HBM4 base die.
Micron confirmed this stupidity in their earnings call and presentation.
This is next-level stupidity. Legit could not believe they had done this when the rumors started spreading a month ago.
Will explain the engineering reasons why this decision is equivalent to Micron shooting themselves in the foot with a rocket launcher later.
For now, you just need to know these rumors happened.
(it explains Micron’s behavior on the calls)
[2] Earnings Call
You will notice a pattern fairly quickly.
First mention of 11 Gbps per pin in prepared remarks.
Timmy floats the word “rumor” to invoke the second mention of 11 Gbps.
We all see what you did there Timmy.
We all know which rumor you are really thinking about.
This includes Sanjay.
Vivek Arya asks the same question but in a different way.
Once again, 11 Gbps is shoved into the response.
Harlan is much more direct.
Once again, 11 Gbps comes up.
Internal logic base die built on a DRAM process node **IS NOT A COMPETATIVE ADVNATAGE**.
It is cheaper. That’s it. Worse performance. Worse power.
Dude is so nervous he is repeating himself over and over LMAO.
Bro if you have industry leading performance why are you not sold out yet?
It’s not a unique advantage.
It is unique self-inflicted disaster.
[3] Callback (second call to feed sell-side more bullshit)
Sometimes, companies hold a second earnings call, commonly referred to as a callback.
They may feel the need to feed sell-side more bullshit than a single 1-hour earnings call can handle.
I am proud to contribute to this “chatter”.
Wait till I teach all the finance people how parametric yield and speed binning works.
Heay he really did go out of his way to shill these numbers.
Imagine claiming you have the best performance HBM4 and getting zero volume orders from Nvidia.
That would be embarrassing if it came to pass.
[4] Memory-based Logic HBM Base Die
Process nodes for DRAM (memory) are radically different from logic process nodes.
Primarily, the physical differences are due to a 1:1 ratio of transistors and capacitors, with a generally low speed requirement for the transistors.
A Background-Proof Guide on Process Development Kits
Irrational Analysis is heavily invested in the semiconductor industry.
You can check out the above post for a technical deep-dive on logic process nodes. I had to use like 5 textbooks to develop the material.
In the interest of not re-writing material, I will keep this section very brief.
DRAM process nodes are designed to make lots of capacitors, and some mediocre transistors
This is very different than logic process nodes which have huge transistor libraries and offer ultra-fast transistor standard cells.
[5] Parametric Yield Crash Course
Since Micron is so keen on letting everyone know how fast their chips THEORETICALLY CAN GO and how they definitely sent Nvidia 11 Gbps samples, let’s talk about how real chip quality distributions work.
Post-silicon validation of logic chips requires testing against PVT corners.
Process
Voltage
Temperature
Let’s start with process.
CMOS means there are N-MOS and P-MOS transistors.
You don’t need to know what these mean. There are two types of transistors, and each have their own characteristics.
A “FF” chip means that the N-MOS and P-MOS transistors are both faster than expected.
Typically, a lot of corner devices is produced by the fab at +/- 2 sigma.
This is accomplished by slowly running wafers through the process node and intentionally over/under-doping parts of the same wafer.
The “characterization lot” is then tested and tuned to maximize yield across target temperature and voltage conditions.
Examples of PVT Corners:
FF device at +10% voltage and 125C die temp.
Hottest corner.
Worst (highest) power consumption.
SS device at -10% voltage and -40C die temp.
Slowest corner.
Transistors speed issues —> timing instability
SF/FS corner at -10% voltage and 125C die temp.
“Skewed” corner that might have some circuits unstable but others completely fine.
Annoying problems happen here.
What I described above is a high-level overview of how-post silicon validation works at a functional level.
For performance, there is a tool called a Shmoo plot.
(yes that is the real name)
https://en.wikipedia.org/wiki/Shmoo_plot
Take two parameters of interest, say voltage and frequency.
Test a device while sweeping the voltage and measuring the maximum stable clock speed.
Do this for many devices and you get a distribution, typically a vanilla gaussian.
(if it is not gaussian, something interesting happened)
Let’s go over a quick example to help you build intuition.
(ALL OF THESE NUMBERS ARE MADE UP)
Suppose you have some arbitrary logic chip.
70% of the chips can meet the target clock speed of 1 GHz, at 0.75 V.
Unfortunately, your customer wants 1.3 GHz and has a strict power limit.
What to do? Consult the Shmoo!
50% of chips can hit 1.3 GHz at 0.9V.
Unfortunately, this voltage is way too high and all the chips blow past the customers maximum power (thermal) spec.
Well.. 10% of chips can hit 1.3 GHz at 0.8V.
Customer is happy with specs, but rather disappointed by the low volume.
Finance department is not happy with negative gross margins.
Somebody is going to be fired.
[6] Interrogation Guide for Financial Professionals
Finance friends, let us go back in time 3 months to Micron’s FQ3 2025 earnings presentation.
2.0 TB/s = 8 Gbps per pin.
So Micron designed their HBM4 base die (using internal “logic/CMOS” process node which is a derivative of DRAM process node) to “exceed” JEDEC spec of 8 Gbps per pin.
In the last three months, Nvidia raised the bar to 11 Gbps.
So what does that mean for the poor DRAM-node transistors Micron is trying to recycle because they are too cheap to use a real logic node like SK Hynix or Samsung?
Nyquist rate is half the datarate.
So Nvidia effectively raised the clock speed requirement from 4 GHz to 5.5 GHz.
In theory, it is possible to use interleaving to reduce the max clock speed most of the transistors need to run at, but I doubt the memory people know how to do this.
Key Points:
Micron HBM4 internal base die parametric yield should be dramatically worse at 5.5 GHz (11 Gbps) versus 4 GHz (8 Gbps).
Micron management chose their words VERY CAREFULLY on both the calls.
They are telling the truth that 11 Gbps samples were delivered.
They are also telling the truth that those samples don’t have power issues.
IF YOU SEND THE TOP X% OF DIES AS SAMPLES (where x is a very small, economically unviable number) TO THE CUSTOMER IT DOES NOT MATTER.
It is a farce.
I am very experienced with logic semiconductor characterization. There is no way Micron’s HBM4 yield is economically viable at 11 Gbps, given the terrible process node handicap and the insane levels of cope expressed in these conference calls.
They tried to save money, and it backfired catastrophically.
They are panicking.
I hereby summon every financial professional who reads my shitposts to go ask Micron management about the parametric yield of their “innovative internal CMOS HBM4 base die using derivative DRAM process node”.
Buy-side
Sell-side (some of the people on the conference calls are 5-star subs… I KNOW YOU HERE)
hedge fund
long-only
family office
Here are some question templates I have prepared for you.
[Template #1] Given that the Q3 2025 earnings deck showed speeds “exceeding” 8 Gbps, it is clear that Micron performed characterization, yield analysis, and speed-binning assuming high-volume customers would purchase at or near those speeds.
With the bar raised to 11 Gbps, how does Micron see parametric yield? If say 70% of base die passed the previous spec, what % passes the new spec. Perhaps you can provide this information in the form of a ratio to keep sensitive information private?
Say the old parametric yield was 50% and the new yield is 10%. That would result in a “yield ratio” of 1/5.
[Template #2] Sumit Sadana said there is “chatter” on the performance of Micron’s HBM4. Can you provide Shmoo plots to address this chatter?
[Template #3] Given that Micron has zero experience with high-performance logic process node development, how has Micron achieved 5.5 GHz FMAX at high yield? The starting point of the “advanced CMOS internal logic process” at Micron was very likely based on a DRAM process node optimized for capacitor density with minimal focus on transistor speed. How has Micron rapidly developed this technology in-house?
[Template #4] Other than cost, what technical advantages does the “advanced CMOS internal logic process” at Micron provide? Logically, external process nodes from logic foundries with decades of experience in high-speed transistor design should have much better PPA (power, performance, area) characteristics, given the decades of experience and cumulative iteration.
What I heard matches as well. Right now, only a very small number of Micron’s HBM4 can actually reach 11Gbps.
I can’t talk about the gate pitch for obvious reasons.
14 is finfet so it’s even older tech node.
From this article thier new 1gamma uses highk metal gate which are 45-28nm
https://assets.micron.com/adobe/assets/urn:aaid:aem:a1133dcd-40d3-49f6-9d56-0d3fbc22527f/renditions/original/as/1-gamma-technology-brief.pdf