Marvell PCIe 7 Switch: Existential Threat to Astera Labs
DesignCon demos have given away what is coming!
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Marvell is working on a PCIe switch. They are very far along in the development. I am 99% confident on this after seeing several incredible demos ad DesignCon.
Before getting started, my biases.
I have lost a lot of money trying to short ALAB 0.00%↑.
I have made a lot of money trading MRVL 0.00%↑ options.
I currently have a small covered call (buy-write) position in Astera Labs.
At the time of writing have hold no position in Marvell stock or options but reserve the right to trade both ALAB 0.00%↑ and MRVL 0.00%↑ at any time without warning.
Contents:
Analysis of DesignCon Demos
PCIe Switch Market Overview
Someone warn Gavin Baker lmao!
[1] Analysis of DesignCon Demos
There were two Marvell TSMC N3 PCIe 7 demos at that stood out to me…
43 dB insertion loss
1.6e-10 pre-FEC bit-error rate.
No active cooling.
45 dB insertion loss
1.7e-8 pre-FEC bit-error rate.
No active cooling.
No Tx FIR! Extreme strain on receiver!
Remember that official PCIe 7 spec is 1e-6 pre-FEC BER at a 36 dB bump-bump insertion loss.
I have a detailed post on communication systems.
A Background-Proof Guide on Communication Systems
Irrational Analysis is heavily invested in the semiconductor industry.
Please read it if you are interested in the technical/engineering background.
The conclusion is simple…
Marvell PCIe 7 SerDes is KICKASS. This is incredible. I cannot express how impressive this is.
It’s so amazing, I spent most of the conference trying to figure out as much as possible. Thankfully, one of the booths gave me permission to take a picture.
This PCB is extremely suspicious. It is highly unusual to have connectors where the Rx (receiver) traces are removed.
The only logical justification I can think of is that Marvell wants to stress test Tx crosstalk… which is a problem in switches.
Furthermore, the demo GUI clearly displayed “FPGA version”. There are no FPGAs on the board so there must be an integrated FPGA on die. This too is highly unusual for a SerDes test chip. I think they are using FPGA logic to try out simple (reduced scale) switching digital logic.
This test chip is an old trial run of a PCIe switch product. Marvell probably already has a full PCIe 7 switch sampling to customers privately.
[2] PCIe Switch Market Overview
For a long time, PCIe switches were effectively an AVGO 0.00%↑ monopoly. Astera Labs saw an opportunity with Amazon (largest customer) and Nvidia AI server head nodes. They made a niche PCIe switch (Scorpio-P) that has the perfect product market fit.
Half the price of competing Broadcom PCIe switch.
Has exactly the number of lanes needed for AI head nodes.
Amazon has a ton of warrants (call options) that exercise if they buy a lot of chips from Astera Labs and Amazon hates Broadcom.
The funny thing is, nothing prevents Broadcom or Marvell from being a fast-follower and making the same niche product.
Broadcom is busy with semi-custom silicon from their innovative 3.5D platform and seems to be ignoring PCIe switches.
Marvell is not. They are coming for Astera Labs lunch!
Importantly, Broadcom and Marvell both make their own excellent in-house SerDes while Astera Labs licenses lower-quality SerDes from a supplier.
The SerDes they use is so weak, every connection needs a retimer chip, increasing BOM cost and reducing power efficiency.
Amazon has likely already purchased enough chips to meet their warrent conditions. This would explain why Amazon has abandoned Astera Labs PCIe retimers in favor of Marvell re-timers. (Amazon has a similar warrent agreement with Marvell)
Amazon has a habit of propping up companies they are invested in with purchase-volume based warrents. Look at Rivian stock. Great example of the Amazon warrent cycle. Astera Labs has already lost the Amazon re-timer socket to Marvell. PCIe switch is very likely to be next!
Sell-side is modeling PCIe switches as a majority-Astera market. This is incredibly wrong.
Marvell makes their own SerDes and thus has higher gross margins.
Marvell’s performance is much better, eliminating the need for re-timed connections on every PCIe switch port.
Amazon has new Marvell warrents and no longer has an incentive to purchase inferior chips from Astera Labs.
[3] Someone warn Gavin Baker lmao!
One of the nice things about running this newsletter is the opportunity to meet people I never would have met through my normal engineering dayjob.
Finance people like drama. So lets talk drama!
Gavin baker is one of my favorite people to follow on X/Twitter. He is simultaneously a genius and a moron. It’s remarkable. His intelligence is bimodal. Very rare.
He invested in ALAB 0.00%↑ back when they were private and has since double downed.
One of the reasons I like Gavin Baker so much is his 13F history is unhinged. This dude trades like a degenerate retail trader. Seriously, go check out his 13F history. He opens and liquidates positions in multiple dangerous/toxic stocks each quarter. He must have some kind of setup that exempts him from capital gains taxes
Even last week as the DeepSeek chaos was killing every AI-related stock, Gavin Baker was defending ALAB 0.00%↑ implicitly.
I am going to tag him on X/Twitter but he might not read tagged tweets from a nobody like me.
Financial professionals who are subscribed… please send this to Gavin lol. Someone needs to warn him. I seem to be the only person who noticed what Marvell was actually demoing at DesignCon. The on-die FPGA logic and unusual Tx-only ports on the PCB scream “PCIe switch”.
Marvell is going to eat Astera Labs lunch. Consensus is extremely wrong.
When do you think they adopt PCIe7 ?
Love the cover