Cerebras Supernova 2026: Irrational Recap
Some useful information. Meaningful progress.
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The one-share activist investor campaign continues.
Snipping a recent funny exchange I had with a much larger fellow shareholder of Cerebras.
Yes, Gavin I have seen their patents.
Their yield issue is not defects. Cerebras solved catastrophic yield. Good for them. 100% of wafers function. At what clock speed and power draw (PARAMETRIC YIELD), unclear which is why I had to model the TOTAL COMPOUND YIELD at 20%.
This is the full editable Excel model that I screenshotted in the argument with Gavin. If you think my assumptions are wrong, go edit it and try to get publicly reported hardware gross margin of WSE3 and rumored ASP to align.
Ok on to the event. Most of it was useless with several terrorist attacks against charts, engineering, and basic critical thinking.
But there was some very useful information that is much appreciated.
Also I like Andrew Feldman’s suit.
This chart’s y-axis actually made my blood pressure go up. Whoever made this shit shame on you.
New system has three wafers (same wafer as before) in one much more efficient box.
Looks like it is short enough to have several general-purpose IT equipment (CPU servers, switches) above.
Each wafer also had double I/O. I suspect they doubled the clock speed of the NoC and by extension the I/O.
Highly doubt power is fully disaggregated. Probably the bulk of power delivery is in the front panel modules and final current multiplier stage is on the WSE package/module itself.
Really wish there were more details.
You can see there is only one I/O card at the top. So they got the doubling just from clock speed and made zero design changes.
Doubling clocks but slightly better than half the latency. Must have made some improvements on the FPGA side.
Ok now I am confused again. They either doubled NoC+I/O clock or they started using two edges instead of one. Whatever I/O doubled. They need more gains to steam in KV cache but for disagg I guess it works. Will trust them on that given the rumors I am hearing on the scale of Cerebras disagg planned deployments.
This is still terrible but less terrible than the previous 5 us. Real progress but they still need to work on this. One of Sean’s comments implied they made an IO ASIC to replace the FPGA. It’s unclear. If anyone can confirm this please let me know.
ON HOW MANY WAFERS? YOUR SLIDE IS MISSING SOME IMPORTANT INFORMATION.
Overall, generally happy with the progress they have made.
I/O has meaningfully improved. They are still bottlenecked by this probably but credit where credit is due.
Clock speed has doubled which is not interesting by itself. What interests me is this implies parametric yield is a lot better.
https://en.wikipedia.org/wiki/Shmoo_plot
There are claims of large improvements in thermal design, power delivery, and manufacturability. Seems believable but unclear how much given all we have are some basic renders with very little in terms of proper technical details.
Maybe they will show more useful information at Hot Chips.
Need more information before attempting to update my gross-margin model. Certainly, there is an improvement. Is this enough to get them to healthy 60+% hardware gross margins? I have absolutely no idea.
DRAM shortage. DRAM shortage.
There is a shit-ton of DRAM capacity coming online in the next two years. And weights will migrate from HBM to HBF, increasing fast memory capacity even further.
And as always, thanks for your insights and outlook!