Isn't most of the WSE-3 fleet currently in use by MBZUAI and G42, Cerebras' UAE anchors? If that's the case then it's possible the realized blended ASP for the fleet currently driving hardware GM is much lower than the $700-$800k range you sourced.
That range does seem corroborated by SemiAnalysis. In May they wrote "BoM of the CS-3 system and the KVSS CPU node to $450k USD per rack" after adjusting for higher memory prices. At 42% GM that's a $775k/system floor price given total COGS is more than BoM. Maybe that's closer to the ASP we'll see for the OpenAI ramp.
I think if we see sequential improvements in GM as OpenAI's share of the WSE-3 fleet ramps up in 2027, the takeaway is less likely to be very low packaging yield and more likely to be mix shift from lower realized ASP at anchor deployments towards higher OpenAI ASP.
Any idea on how far along (if they've even started) they are on bonding an SRAM wafer on top of the WSE? I would imagine this is another packaging vector to kill yield because it has to be W2W bonding which is still nascent.
actually W2W yield is much better than die to die if done correctly as examplified by Huawei's tau law scaling. The issue is bump density & density. 6nm-7nm is a nice hybrid bonding density for Huawei to work with but for TSMC at 2-3nm density it is a nightmare even for W2W.
I thought this was well reasoned and I appreciate that low latency coding is a valuable niche. Unfortunately, coming from the semi manufacturing side, wafer scale is heresy and must be purged with fire. It is not different this time.
"can't find examples of where slow has meaningful portions of market"
This strikes me as a silly statement. There's always economic choices being made. Just ask mm-wave 5G how that's working out.
Also if there's any truth behind the headlines about companies getting stingy over token costs, it seems the fast, premium tokens would be the first to go.
And the comments about dodging N3 + HBM constraints -- doesn't this also apply to Groq LPU on SF4? But Jenson didn't make it sound like there was much demand for it.
As far as I can tell, the packaging, including the stitching-together (with millions of tiny wires between each of the reticle-sized sections) is the key challenge for any wafer-scale processors. Has Cerebras made any progress in their packaging between the different generations of their WSE?
I am still confused. Are you bullish or bearish or just don’t know what?
I don’t have a clue what you said or mean. Perhaps a few education episodes explaining what you’re talking about.
Isn't most of the WSE-3 fleet currently in use by MBZUAI and G42, Cerebras' UAE anchors? If that's the case then it's possible the realized blended ASP for the fleet currently driving hardware GM is much lower than the $700-$800k range you sourced.
That range does seem corroborated by SemiAnalysis. In May they wrote "BoM of the CS-3 system and the KVSS CPU node to $450k USD per rack" after adjusting for higher memory prices. At 42% GM that's a $775k/system floor price given total COGS is more than BoM. Maybe that's closer to the ASP we'll see for the OpenAI ramp.
I think if we see sequential improvements in GM as OpenAI's share of the WSE-3 fleet ramps up in 2027, the takeaway is less likely to be very low packaging yield and more likely to be mix shift from lower realized ASP at anchor deployments towards higher OpenAI ASP.
Any idea on how far along (if they've even started) they are on bonding an SRAM wafer on top of the WSE? I would imagine this is another packaging vector to kill yield because it has to be W2W bonding which is still nascent.
actually W2W yield is much better than die to die if done correctly as examplified by Huawei's tau law scaling. The issue is bump density & density. 6nm-7nm is a nice hybrid bonding density for Huawei to work with but for TSMC at 2-3nm density it is a nightmare even for W2W.
disappointing price action……..wonder when it will bounce back
What is the renting cost for a single cs-3 rack per hour according to you is that a viable business for their earning via their cloud?
I thought this was well reasoned and I appreciate that low latency coding is a valuable niche. Unfortunately, coming from the semi manufacturing side, wafer scale is heresy and must be purged with fire. It is not different this time.
"can't find examples of where slow has meaningful portions of market"
This strikes me as a silly statement. There's always economic choices being made. Just ask mm-wave 5G how that's working out.
Also if there's any truth behind the headlines about companies getting stingy over token costs, it seems the fast, premium tokens would be the first to go.
And the comments about dodging N3 + HBM constraints -- doesn't this also apply to Groq LPU on SF4? But Jenson didn't make it sound like there was much demand for it.
I think the packaging yield is well above 50% now
They won't be grow to without chiplet architecture which defeats the whole dinner plate model they use.
Yields will suck when packaging is using poor material. They need to use glass or something to prevent cracking ect.
they are already on fp8
As far as I can tell, the packaging, including the stitching-together (with millions of tiny wires between each of the reticle-sized sections) is the key challenge for any wafer-scale processors. Has Cerebras made any progress in their packaging between the different generations of their WSE?
Sounds to me CBRZ is the right ticker to own lol