Aehr and Micron Catch-Up Note
Aehr Test Systems: Incredibly Stupid Semicap Play
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Still on break.
Once again, one-hour time limit.
“Splinter in your mind” is an accurate description of what the AEHR 0.00%↑ earnings call transcript has done to my brain. This setup is so stupid, so incredibly dangerous, so unhinged that I gotta write it.
First, do not fucking touch the options chain. It is revolting.
Second, understand that this is a truly degenerate, high-risk idea.
Third, “The Alters” is the most incredible video game I have ever played and all of you should go try it even if you literally have never played a video game before in your life.
https://store.steampowered.com/app/1601570/The_Alters/
Also here are updated disclosures. Everything in the trading account.
Aehr:
Look at this graph.
What you need to know is that AEHR 0.00%↑ is the shittiest of shitcos. A silicon-carbide “wafer-level burn-in” meme stock that has a pumper CEO and basically zero professional coverage. All of the finance people have written this one off, and rightfully so.
Until now. There is something that was said in the last earnings call that is incredibly stupid but also seemingly legit that it changes everything.
Aehr’s clown CEO said on the record that there are two hyperscalers who are evaluating wafer-level burn-in of AI logic wafers.
I call him a clown because he is one.
Aehr was subject to a shareholder lawsuit that was only recently dismissed. This idiot literally cannot contain himself. The shit he said on this earnings call probably make any lawyer they have on retainer sweat bullets.
Dude is aware he needs to be careful.
So let’s assume Aehr CEO is not lying about this AI logic wafer-level burn-in thing.
Two hyperscalers seriously evaluating this insane concept.
Let me explain why it is crazy and why I think it could actually be real.
The traditional markets Aehr serves with wafer-level burn-in testing are Silicon-Carbide, Gallium-Nitride, Indium-Phosphide, and so on.
Basically, specialty NON-SILICON/NON-LOGIC wafers.
There is a reason for this lack of exposure to logic.
https://en.wikipedia.org/wiki/High-temperature_operating_life
Normal procedure for logic reliability (HTOL):
Select a random sample of parts (typically 80 or 160 dice).
Run the parts in an oven at high die temperature (typically 125C or 135C) and higher than normal operating voltage (typically +10% or +20% on all rails).
Check on parts periodically, typically at 40, 168, 500, and 1000 hours.
If all parts in the lot still perform “close-enough” to the performance at 0-hour and current draw is also “close-enough” to 0-hour, the design passes HTOL.
Pass HTOL typically means 10-year reliability at nominal operating conditions.
The numbers change based on the design and end-market but the procedure is basically the same for all logic chips. I have literally done this testing before with Incal machines before Aehr bought them.
HTOL is something you do ONCE for a design and NEVER AGAIN. It takes 42 days minimum (1000 hours) and often takes longer because things go wrong. Trust me, I know.
Logic chip designers take great care to simulate circuits (analog and digital) to make sure HTOL (AKA electromigration, AKA “EM”) passes.
If HTOL/EM fails, that requires detailed failure analysis with infrared microscopes, probe stations, and so on… followed by a full re-spin and redoing HTOL from scratch.
Minimum 5-month delay in project timeline.
https://www.ansys.com/blog/what-is-electromigration
A design failing HTOL is a big deal that can easily result in someone losing their job.
Broadly though, the EDA simulation tools are quite good at catching these problems, so long as the designers are disciplined and do their homework.
What if a new class of logic chips (AI ASIC) designed by a new class of inexperienced entities (Hyperscalers ex-Google) were so important that skipping EM simulations and HTOL testing was worth it? What if time-to-market was so critical that two hyperscalers said “Fuck it, just burn in all the logic wafers. CoWoS and HBM are so expensive it makes economic sense.”
I believe this is what is happening.
Wafer-level burn-in is completely irrational, unless you are in such a rush and the COGS from logic wafers is so low (as a % of BOM) that you don’t care.
I shorted Aehr because the CEO was in full degenerate pump mode. Doug told me to listen to the call again and I took his advice. After thinking about it, Doug is probably right. Hell, I am way more bullish than him now. Nobody else seems to have noticed this wafer-level burn-in for logic opportunity because Gayn is the clown CEO who cried wolf[speed] too many times.
I genuinely believe AI ASIC wafer-level burn-in of logic wafers is real and literally nothing else matters for Aehr.
Given this companies track record, the stock is radioactive to basically all professional investors. No way buy-side analysts can pitch this to their PM’s without getting laughed out of the room.
As a degenerate, high-risk idea, Aehr is worth thinking about.
Micron:
Samsung mass-produced HBM3e 12-hi in anticipation of getting finally qualified with Nvidia and they apparently lied to Nvidia for the 6th fucking time.
Now, a huge pile of garbage HBM is sitting in Samsung inventory and they had to write it off in their books.
If Samsung comes clean and re-bins the inventory to meet Nvidia’s power (parametric) specs, Micron is absolutely fucked. Some subset (30%? 50%?) of Samsungs HBM3e 12-hi inventory passes Nvidia spec. Samsung just has to admit to reality and only partially undo the write-off.
MU 0.00%↑ is either going to $160 or $90 depending exclusively on what Samsung deices. Tread lightly.
[Bonus] Marvell Meme:
https://x.com/typedfemale/status/1945912359027114310?t=rAC6vGMkscNmpuy5_QnR6A&s=19
Feeling good about being degenerate today
Nvidia's pace of innovation means you either go for shortcuts and get bricked chips, or by the time you ship products last gen (or even 2 year old) Nvidia chips outperform you on inference. And they get depreciated to a point that whatever your cost savings are, it's not enough to justify using your ASICs.